HDL Works HDL Design Entry EASE v7.3 R7 for Linux 英文正式版(混合語言等電路設計輸入最佳環境軟體
破解說明:
關掉主程式,破解檔放置於crack夾內,請將破解檔複製於主程式的安裝目錄內既可破解
內容說明:
EASE可提供對VHDL、Verilog、FPGA和ASIC的混合語言等電路設計輸入最佳環境，當完成設計後，
允許使用者自行選擇自己喜歡，由EASE提供獨立的合成與模擬工具。在市場上，EASE提供最直覺
的設計輸入環境，而且不管是對初學者或進階者，提供HDL設計所需的特性，可選擇文字方式或圖
形方式進行設計，EASE會自動依你選擇的編程語言將圖形轉換成對應的HDL語言。
VHDL(VHSIC Hardware description language-高速積體電路描述語言；VHSIC- Very High Speed
Integrated Circuit：高速積體電路)
英文說明:
EASE offers the best of both worlds with your choice of graphical or
text based HDL entry. You don?t need to be a master of either Verilog
or VHDL. When you're creating a new design, just enter your design using
your mix of graphics and text. EASE automatically generates optimized
HDL code for you in the selected language - VHDL or Verilog. Industry
standard version control environments deal with design and configuration
management enabling multiple users to work simultaneously on one EASE
project.
Features & Benefits
- Graphical design environment with automated generation of hierarchical
VHDL or Verilog code
- Push-button import of legacy Verilog or VHDL designs and extraction of
graphical hierarchy
- Adheres to state of the art Windows look and feel for intuitive operation
- Standards compliant (IEEE-1076-87&93 VHDL and IEEE-1364 Verilog)
- True multi-user design environment and associated version control,
managed by a sophisticated design environment browser
- Integrates smoothly with the industry's most popular simulators and
synthesis tools
- Platform independent database
- Integrated HDL language editor
- Hot error reporting
圖片說明:
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